Scheduling blocks of hierarchical compiled simulation of combinational circuits
نویسندگان
چکیده
منابع مشابه
Scheduling Blocks for Hierarchical Compiled Simulation
Although preserving the hierarchy in compiled simulation can significantly reduce the compilation time for the code generated by the circuit compiler, the possibility of introducing pseudo-cycles due to element grouping can impair the performance of the generated code. A new approach to this problem is presented which uses dependency information to reduce the number of times a particular block ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 1991
ISSN: 0278-0070
DOI: 10.1109/43.68405